HDL based FPGA interface library for data acquisition and multipurpose real time algorithm processing

• Type: Article in International Conference Proceedings Book
• Date: 2010

Authors

Fernandes, AM (Author) Other; Pereira, RC (Author) Other; Sousa, J (Author) Other; Batista, AJN (Author) Other; Combo, A (Author) Other; Carvalho, BB (Author) Other; Correia, CMBA (Author) Other; Varandas, CAF (Author) Other

Conference proceedings International

Title: Conference Record - 2010 17th IEEE-NPSS Real Time Conference, RT10

2010 17th IEEE-NPSS Real Time Conference, RT10

Lisbon, 24 May 2010 through 28 May 2010

Indexing

Scopus - 1 Citation

Other information

Authenticus ID: P-007-YCK

DOI: 10.1109/rtc.2010.5750400

Abstract (EN): The inherent parallelism of the logic resources, the flexibility in its configuration and the performance at high processing frequencies makes the field programmable gate array (FPGA) the most suitable device to be used both for real time algorithm processing and data transfer in instrumentation modules. Moreover, the reconfigurability of these FPGA based modules enables exploiting different applications on the same module. When using a reconfigurable module for various applications, the availability of a common interface library for easier implementation of the algorithms on the FPGA leads to more efficient development. The FPGA configuration is usually specified in a hardware description language (HDL) or other higher level descriptive language. The critical paths, as the management of internal hardware clocks, that require deep knowledge of the module behavior shall be implemented in HDL to optimize the timing constraints. The common interface library should include these critical paths, freeing the application designer from hardware complexity and able to choose any of the available high-level abstraction languages for the algorithm implementation. With this purpose a modular Verilog code was developed for the Virtex 4 FPGA of the in-house Transient Recorder and Processor (TRP) hardware module, based on the Advanced Telecommunications Computing Architecture (ATCA), with eight channels sampling at up to 400 MSamples/s. The TRP was designed to perform real time Pulse Height Analysis (PHA), Pulse Shape Discrimination (PSD) and Pile-Up Rejection (PUR) algorithms at a high count rate (few MHz). A brief description of this modular code is presented and examples of its use as interface with end user algorithms, including a PHA with PUR, are described. © 2010 IEEE.

Language: English

Type (Professor's evaluation): Scientific