Architecture for Transparent Binary Acceleration of Loops with Memory Accesses

• Type: Article in International Conference Proceedings Book
• Date: 2013

Authors

Nuno Paulino (Author) FEUP; João Canas Ferreira (Author) FEUP; João Cardoso (Author) FEUP

Conference proceedings International

Title: RECONFIGURABLE COMPUTING: ARCHITECTURES, TOOLS AND APPLICATIONS

Pages: 122-133

9th International Applied Reconfigurable Computing Symposium (ARC)

Los Angeles, CA, MAR 25-27, 2013

Indexing

ISI Web of Knowledge - 1 Citation

Scopus - 2 Citations

Scientific classification

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

Authenticus ID: P-008-A38

DOI: 10.1007/978-3-642-36812-7_12

Abstract (EN): This paper presents an extension to a hardware/software system architecture in which repetitive instruction traces, called Megablocks, are accelerated by a Reconfigurable Processing Unit (RPU). This scheme is supported by a custom toolchain able to automatically generate a RPU tailored for the execution of one or more Megablocks detected offline. Switching between hardware and software execution is done transparently, without modifications to source code or executable binaries. Our approach has been evaluated using an architecture with a MicroBlaze General Purpose Processor (GPP) softcore. By using a memory sharing mechanism, the RPU can access the GPP's data memory, allowing the acceleration of Megablocks with load/store operations. For a set of 21 embedded benchmarks, an average speedup of 1.43x is achieved, and a potential speedup of 2.09x is predicted for an implementation using a low overhead interface for communication between GPP and RPU.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 12