Algorithms for run-time placement and routing on Virtex II Pro FPGAs

• Type: Article in International Conference Proceedings Book
• Date: 2010

Authors

Miguel L. Silva (Author) FEUP; João Canas Ferreira (Author) FEUP

Conference proceedings National

Title: Actas das VI Jornadas sobre Sistemas Reconfiguráveis - REC'2010

Pages: 9-16

VI Jornadas sobre Sistemas Reconfiguráveis (REC'2010)

Aveiro, 4 a 5 de Fevereiro, 2010

Scientific classification

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

CORDIS: Technological sciences > Engineering > Computer engineering ; Technological sciences > Engineering > Electronic engineering

Other information

Abstract (EN): Run-time reconfiguration is a useful approach to the implementation of highly-adaptive embedded systems. To generate partial bitstreams at run-time for dynamic reconfiguration of sections of a platform FPGA we combine partial bitstreams of coarse-grained components specified by an acyclic netlist. The placement an routing algorithm play and essential role on the generation of partial bitstreams. A greedy placement heuristic based on topological sorting is used to determine the positions of individual components, and a router based on non-backtracking search over restricted areas determines the routes for the interconnections. The approach is validated with a set of 35 benchmarks (both synthetic and application-derived) having between three and 41 components, the complete process of bitstream generation takes between 7s and 101s (average 48.3s) when running on an embedded PowerPC 405 microprocessor clocked at 300MHz.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 8