Test chip for the development and evaluation of sensors for measuring stress in metal interconnect

• Type: Article in International Scientific Journal
• Date: 2005

Authors

dos Santos, J.M.M. (Author) Other

Journal

Title: IEEE Transactions on Semiconductor Manufacturing

Vol. 18 No. 2

Pages: 255-261

ISSN: 0894-6507

Publisher: IEEE

Indexing

ISI Web of Science

Scientific classification

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

CORDIS: Technological sciences > Technology > Micro-technology > Microsystems

Other information

Abstract (EN): The development of a new test chip is presented, containing structures for the direct measurement of stress in metallic interconnect layers associated with silicon integrated circuit technology. The rotation of the structures provides a simple method of differentiating between tensile and compressive stress. This test chip design has been used to fabricate working structures allowing the study of stresses in aluminum layers before and after sample sintering. The results are presented together with the design, fabrication, and measurement considerations that have arisen during the research. The problems experienced in removing the sacrificial layer material, necessary to release the structures, are discussed along with potential solutions. The sensor structure is suitable for fabrication within a CMOS facility and its inherent scalability makes it potentially suitable for in-line testing of state-of-the-art processes

Language: Portuguese

Type (Professor's evaluation): Scientific