Generation of Coarse-Grained Reconfigurable Processing Units for Binary Acceleration

• Type: Article in International Conference Proceedings Book
• Date: 2012

Authors

Nuno Paulino (Author) FEUP; João Canas Ferreira (Author) FEUP; João M. P. Cardoso (Author) FEUP

Conference proceedings National

Title: Actas das VIII Jornadas sobre Sistemas Reconfiguráveis (REC 2012)

Pages: 11-19

VIII Jornadas sobre Sistemas Reconfiguráveis (REC 2012)

Lisboa, Portugal, 9 a 10 de Fevereiro de 2012

Scientific classification

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

CORDIS: Technological sciences > Engineering > Computer engineering

Other information

Abstract (EN): This paper presents two architectural variants of a runtime reconfigurable architecture aimed at the transparent acceleration of embedded programs. Starting from Control/ Data Flow Graphs (CDFGs) representing Megablocks, i.e., repetitive single-path sequences of instructions, extracted from MicroBlaze instruction traces, the implemented tool chain generates a Reconfigurable Processing Unit (RPU) tailored for the detected Megablocks. The RPUs generated consist of a 2D array of functional units and act as hardware accelerators capable of executing multiple Megablocks according to the current configuration. Use of the RPU is completely transparent, i.e., does not require modifying the CPU or the application. The RPU triggering mechanism is coupled to an external memory bus in the first variant of the architecture, and to a Local Memory Bus (LMB) in the second. The speedups measured on a Spartan-6 FPGA for a set of benchmarks range from 2.25 to 43.37 for the external-memory-based variant and from 0.63 to 3.60 for the LMB-based version.

Language: English

Type (Professor's evaluation): Scientific