Improving Run-Time Creation of Partial FPGA Configurations

• Type: Article in International Conference Proceedings Book
• Date: 2011

Authors

Miguel L. Silva (Author) FEUP; João Canas Ferreira (Author) FEUP

Conference proceedings National

Title: Actas das VII Jornadas sobre Sistemas Reconfiguráveis (REC 2011)

Pages: 57-64

VIII Jornadas sobre Sistemas Reconfiguráveis (REC 2011)

Porto, 3 a 4 de Fevereiro de 2011

Scientific classification

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

CORDIS: Technological sciences > Engineering > Electronic engineering ; Technological sciences > Engineering > Computer engineering

Other information

Abstract (EN): This paper describes and evaluates improvements to a previously-reported method to generate partial FPGA configurations at run-time. The system is intended for use in adaptive embedded systems that employ run-time reconfiguration to achieve high flexibility and performance. The new version handles components netlists with cycles, improves placement by adding an optimization step based on simulated annealing, speeds-up routing by re-using previously created routes and eliminates restrictions on the positions of component terminals. The proof-of-concept implementation running in a Virtex-II Pro FPGA reduces execution time by more than 50% (on average) for a set of 30 benchmark circuits. The complete configuration creation process takes between 3.9s and 38.3s.

Language: English

Type (Professor's evaluation): Scientific