Exploiting the Run-Time Use of IP Cores on Dynamically Reconfigurable Systems

• Type: Article in International Conference Proceedings Book
• Date: 2008

Authors

Miguel L. Silva (Author) FEUP; João Canas Ferreira (Author) FEUP

Conference proceedings National

Title: Actas das 4.as Jornadas sobre Sistemas Reconfiguráveis

Pages: 31-37

Jornadas Sobre Sistemas Reconfiguráveis (REC'2008)

Braga, 7 a 8 de Fevereiro de 2008

Scientific classification

FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering

Other information

Abstract (EN): The advantages of dynamic reconfiguration can only be exploited if devices, tools and design flows are available to support the partial reconfiguration of FPGA-based systems. For a number of applications, enabling the swap of cores at run-time, under software control, is an essential feature that allows tailoring the system response to the needs of different methods, standards and power/performance requirements. The paper proposes a method to support the exchange of intellectual property (IP) cores during system operation. The approach is based on the definition of a base system, with reserved or dynamic areas, where different cores may be plugged in, providing time-sharing of the system resources. It is shown how BitLinker, a tool developed to handle and assemble bitstream-level IP cores, can be used in a design flow that allows different cores to be used in one or more host areas, with a minimal intervention of the designer. An application example is also presented to illustrate the concept.

Language: Portuguese

Type (Professor's evaluation): Scientific