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A new approach to assess defragmentation strategies in dynamically reconfigurable FPGAs

Title
A new approach to assess defragmentation strategies in dynamically reconfigurable FPGAs
Type
Article in International Conference Proceedings Book
Year
2006
Authors
Manuel G. Gericota
(Author)
Other
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Gustavo R. Alves
(Author)
Other
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Luís F. Lemos
(Author)
Other
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José M. Ferreira
(Author)
FEUP
Conference proceedings International
Pages: 262-267
Second International Workshop on Applied Reconfigurable Computing (ARC 06)
Delft, The Netherlands, 1 a 3 de Março de 2006
Indexing
Publicação em ISI Web of Science ISI Web of Science
Publicação em Scopus Scopus
INSPEC
Scientific classification
FOS: Engineering and technology > Electrical engineering, Electronic engineering, Information engineering
Other information
Abstract (EN): Fragmentation on dynamically reconfigurable FPGAs is a major obstacle to the efficient management of the logic space in reconfigurable systems. When resource allocation decisions have to be made at run-time a rearrangement may be necessary to release enough contiguous resources to implement incoming functions. The feasibility of run-time relocation depends on the processing time required to set up rearrangements. Moreover, the performance of the relocated functions should not be affected by this process or otherwise the whole system performance, and even its operation, may be at risk. Relocation should take into account not only specific functional issues, but also the FPGA architecture, since these two aspects are normally intertwined. A simple and fast method to assess performance degradation of a function during relocation and to speed up the defragmentation process, based on previous function labelling and on the application of the Euclidian distance concept, is proposed in this paper.
Language: English
Type (Professor's evaluation): Scientific
No. of pages: 6
License type: Click to view license CC BY-NC
Documents
File name Description Size
75.C-ARC_2006_56052 A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs 158.67 KB
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