Go to:
Logótipo
Comuta visibilidade da coluna esquerda
Você está em: Start > Publications > View > FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example
Publication

Publications

FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example

Title
FPGAs as General-Purpose Accelerators for Non-Experts via HLS: The Graph Analysis Example
Type
Article in International Conference Proceedings Book
Year
2021
Authors
Silva, PF
(Author)
Other
The person does not belong to the institution. The person does not belong to the institution. The person does not belong to the institution. Without AUTHENTICUS Without ORCID
Nuno Paulino
(Author)
FEUP
View Personal Page You do not have permissions to view the institutional email. Search for Participant Publications View Authenticus page View ORCID page
Conference proceedings International
Pages: 102-105
20th International Conference on Field-Programmable Technology, ICFPT 2021
6 December 2021 through 10 December 2021
Other information
Authenticus ID: P-00V-V3R
Abstract (EN): We discuss the concept of FPGA-unfriendliness, the property of certain algorithms, programs, or domains which may limit their applicability to FPGAs. Specifically, we look at graph analysis, which has recently seen increased interest in combination with High-Level Synthesis, but has yet to find great success compared to established acceleration mechanisms. To this end, we make use of Xilinx's Vitis Graph Library to implement Single-Source Shortest Paths (SSSP) and PageRank (PR), and present a custom kernel written from the ground up for Distinctiveness Centrality (DC, a novel graph centrality measure). We use public datasets to test these implementations, and analyse power consumption and execution time. Our comparisons against published data for GPU and CPU execution show FPGA slowdowns in execution time between around 18.5x and 328x for SSSP, and around 1.8x and 195x for PR, respectively. In some instances, we obtained FPGA speedups versus CPU of up to 2.5x for PR. Regarding DC, results show speedups from 0.1x to 3.5x, and energy efficiency increases from 0.8x to 6x. Lastly, we provide some insights regarding the applicability of FPGAs in FPGA-unfriendly domains, and comment on the future as FPGA and HLS technology advances.
Language: English
Type (Professor's evaluation): Scientific
No. of pages: 4
Documents
We could not find any documents associated to the publication.
Related Publications

Of the same authors

Building Beyond HLS: Graph Analysis and Others (2021)
Other Publications
Silva, PF; João Bispo; Nuno Paulino
Recommend this page Top
Copyright 1996-2025 © Faculdade de Direito da Universidade do Porto  I Terms and Conditions  I Acessibility  I Index A-Z
Page created on: 2025-07-10 at 11:07:51 | Privacy Policy | Personal Data Protection Policy | Whistleblowing