Graph-Based Code Restructuring Targeting HLS for FPGAs

• Type: Article in International Conference Proceedings Book
• Date: 2019

Authors

Afonso Canas Ferreira (Author) FEUP; João Manuel P. Cardoso (Author) FEUP

Conference proceedings International

Title: Applied Reconfigurable Computing - 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9-11, 2019, Proceedings

Pages: 230-244

15th International Symposium on Applied Reconfigurable Computing, ARC 2019

9 April 2019 through 11 April 2019

Indexing

Scopus - 1 Citation

Other information

Authenticus ID: P-00Q-CFQ

DOI: 10.1007/978-3-030-17227-5_17

Abstract (EN): High-level synthesis (HLS) is of paramount importance to enable software developers to map critical computations to FPGA-based hardware accelerators. However, in order to generate efficient hardware accelerators one needs to apply significant code transformations and adequately use the directive-driven approach, part of most HLS tools. The code restructuring and directives needed are dependent not only of the characteristics of the input code but also of the HLS tools and target FPGAs. These aspects require a deep knowledge about the subjects involved and tend to exclude software developers. This paper presents our recent approach for automatic code restructuring targeting HLS tools. Our approach uses an unfolded graph representation, which can be generated from program execution traces, and graph-based optimizations, such as folding, to generate suitable HLS C code. In this paper, we describe the approach and the new optimizations proposed. We evaluate the approach with a number of representative kernels and the results show its capability to generating efficient hardware implementations only achievable using manual restructuring of the input software code and manual insertion of adequate HLS directives. © 2019, Springer Nature Switzerland AG.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 15