A First Performance Analysis of the Admission Control in the HaRTES Ethernet Switch

• Type: Article in International Conference Proceedings Book
• Date: 2016

Authors

Alvarez, I (Author) Other; Knezic, M (Author) Other; Luis Almeida (Author) FEUP; Proenza, J (Author) Other

Conference proceedings International

Title: 2016 IEEE 21ST INTERNATIONAL CONFERENCE ON EMERGING TECHNOLOGIES AND FACTORY AUTOMATION (ETFA)

Pages: 1-4

21st IEEE International Conference on Emerging Technologies and Factory Automation (ETFA)

OWL Univ Appl Sci, Fraunhofer IOSB INA, Berlin, GERMANY, SEP 06-09, 2016

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Other information

Authenticus ID: P-00M-85Q

DOI: 10.1109/etfa.2016.7733688

Abstract (EN): There is a growing interest in developing embedded systems capable of being deployed in dynamic environments that may change in unpredictable manners. When such systems are Distributed Embedded Systems (DESs) they must exhibit flexibility at all levels of their architecture, including the network. On the other hand, there is a clear trend in industry towards using Ethernet-based protocols at the network level of DESs. Nevertheless, Ethernet lacks appropriate support for real-time (RT) communications, mixing different RT traffic and on-line management of the Quality of Service (QoS). Several implementations of the Flexible Time-Tiggered (FTT) protocol over Ethernet were proposed to cope with these drawbacks. FTT is a master/multi-slave protocol that is able to simultaneously convey real and non-real-time traffic and provides mechanisms for dynamically changing the QoS of the network, including Admission Control (AC). The AC is a fundamental component for on-line network management, since it guarantees that each participant gets the required QoS. This paper presents the implementation in OMNeT++ of a simulation model of the AC in the FTT HaRTES switch as well as a preliminary performance study using that model.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 4