Scalable hardware architecture for disparity map computation and object location in real-time

• Type: Article in International Scientific Journal
• Date: 2016

Authors

Santos, PM (Author) Other; João Canas Ferreira (Author) FEUP; José Silva Matos (Author) FEUP

Journal

Title: Journal of Real-Time Image Processing

Vol. 11

Pages: 473-485

ISSN: 1861-8200

Publisher: Springer Nature

Indexing

ISI Web of Knowledge - 2 Citations

Scopus - 3 Citations

Other information

Authenticus ID: P-008-NXM

DOI: 10.1007/s11554-013-0338-1

Abstract (EN): We present the disparity map computation core of a hardware system for isolating foreground objects in stereoscopic video streams. The operation is based on the computation of dense disparity maps using block-matching algorithms and two well-known metrics: sum of absolute differences and Census transform. Two sets of disparity maps are computed by taking each of the images as reference so that a consistency check can be performed to identify occluded pixels and eliminate spurious foreground pixels. Taking advantage of parallelism, the proposed architecture is highly scalable and provides numerous degrees of adjustment to different application needs, performance levels and resource usage. A version of the system for 640 x 480 images and a maximum disparity of 135 pixels was implemented in a system based on a Xilinx Virtex II-Pro FPGA and two cameras with a frame rate of 25 fps (less than the maximum supported frame rate of 40 fps on this platform). Implementation of the same system on a Virtex-5 FPGA is estimated to achieve 80 fps, while a version with increased parallelism is estimated to run at 140 fps (which corresponds to the calculation of more than 5.9 x 10(9) disparity-pixels per second).

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 13