Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems

• Type: Article in International Scientific Journal
• Date: 2007

Authors

Silva, ML (Author) Other; João Canas Ferreira (Author) FEUP

Journal

Title: IET Computers and Digital Techniques

Vol. 1 No. 5

Pages: 461-471

ISSN: 1751-8601

Publisher: Wiley-Blackwell

Indexing

ISI Web of Knowledge - 5 Citations

Scopus - 5 Citations

Other information

Authenticus ID: P-004-7ST

DOI: 10.1049/iet-cdt:20060056

Abstract (EN): A tool called BITLINKER, that creates partially reconfigurable modules from the bit-streams of individual components is described. It is also capable of performing restricted component placement and interconnect routing between the assembled components. The resulting modules are used in applications that exploit partial dynamic reconfiguration. The tool is integrated in a design flow particularly aimed at dynamically reconfigurable platform field-programmable gate arrays (FPGAs). The associated development design flow and a run-time support system that can be used to manage module activation and data communication are described. Evaluation results obtained with a Virtex-II Pro system are also reported.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 11