Pipelining data-dependent tasks in FPGA-based multicore architectures

• Type: Article in International Scientific Journal
• Date: 2016

Authors

Azarian, A (Author) Other; João M. P. Cardoso (Author) FEUP

Journal

Title: Microprocessors and Microsystems

Vol. 42

Pages: 165-179

ISSN: 0141-9331

Publisher: Elsevier

Indexing

ISI Web of Knowledge - 0 Citations

Scopus - 0 Citations

Other information

Authenticus ID: P-00K-BGG

DOI: 10.1016/j.micpro.2016.02.008

Abstract (EN): In recent years, there has been increasing interest in using task-level pipelining to accelerate the overall execution of applications mainly consisting of producer/consumer tasks. This paper proposes fine- and coarse-grained data synchronization approaches to achieve pipelining execution of producer/consumer tasks in FPGA-based multicore architectures. Our approaches are able to speedup the overall execution of successive, data-dependent tasks, by using multiple cores and specific customization features provided by FPGAs. An important component of our approach is the use of customized inter-stage buffer schemes to communicate data and to synchronize the cores associated with the producer/consumer tasks. We propose techniques to reduce the number of accesses to external memory in our fine-grained data synchronization approach. The experimental results show the feasibility of the approach in both in-order and out-of-order producer/consumer tasks. Moreover, the results using our approach reveal noticeable performance improvements for a number of benchmarks over a single core implementation without using task-level pipelining.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 15