Coarse/Fine-grained Approaches for Pipelining Computing Stages in FPGA-Based Multicore Architectures

• Type: Article in International Conference Proceedings Book
• Date: 2014

Authors

Azarian, A (Author) Other; João M. P. Cardoso (Author) FEUP

Conference proceedings International

Title: EURO-PAR 2014: PARALLEL PROCESSING WORKSHOPS, PT II

Pages: 266-278

20th Euro-Par International Workshops

Porto, PORTUGAL, AUG 25-26, 2014

Indexing

ISI Web of Knowledge - 2 Citations

Scopus - 2 Citations

Other information

Authenticus ID: P-00A-4JB

DOI: 10.1007/978-3-319-14313-2_23

Abstract (EN): In recent years, there has been increasing interest on using task-level pipelining to accelerate the overall execution of applications mainly consisting of producer/consumer tasks. This paper presents coarse/fine-grained data flow synchronization approaches to achieve pipelining execution of the producer/consumer tasks in FPGA-based multicore architectures. Our approaches are able to speedup the overall execution of successive, data-dependent tasks, by using multiple cores and specific customization features provided by FPGAs. An important component of our approach is the use of customized inter-stage buffer schemes to communicate data and to synchronize the cores associated to the producer/consumer tasks. The experimental results show the feasibility of the approach when dealing with producer/consumer tasks with out-of-order communication and reveal noticeable performance improvements for a number of benchmarks over a single core implementation and not using task-level pipelining.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 13