Reducing Misses to External Memory Accesses in Task-Level Pipelining

• Type: Article in International Conference Proceedings Book
• Date: 2015

Authors

Azarian, A (Author) Other; João M. P. Cardoso (Author) FEUP

Conference proceedings International

Title: 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)

Pages: 1422-1425

IEEE International Symposium on Circuits and Systems (ISCAS)

Lisbon, PORTUGAL, MAY 24-27, 2015

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Other information

Authenticus ID: P-00G-SYF

DOI: 10.1109/iscas.2015.7168910

Abstract (EN): Recently, researchers have shown an increased interest in using task-level pipelining to accelerate the overall execution of applications mainly consisting of producer-consumer tasks. This paper proposes optimization techniques for enhancing our approach to pipeline the execution of producer-consumer tasks in FPGA-based multicore architectures with reductions in the number of accesses to external memory. Our approach is able to speedup the overall execution of successive, data-dependent tasks, by using multiple cores and specific customization features provided by FPGAs. We evaluate the impact in the performance of task-level pipelining when using different hash functions and optimization schemes in the inter stage buffer (ISB). The optimizations proposed in this paper were evaluated with FPGA implementations. The experimental results show the efficiency of a simple scheme to reduce external memory accesses and the suitability of the hash function being used. Furthermore, the results reveal noticeable performance improvements for the set of benchmarks being used.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 4