Compilers for Reconfigurable Architectures

• Type: Chapter or Part of a Book
• Date: 2008

Authors

João M. P. Cardoso (Author) FEUP; P. C. Diniz (Author) Other

Book

Title: Compilation Techniques for Reconfigurable Architectures

Pages: 155-176

ISBN: 978-0-387-09670-4

Electronic ISBN: 978-0-387-09671-1

Publisher: Springer

Other information

Authenticus ID: P-00G-ZXQ

DOI: 10.1007/978-0-387-09671-1_6

Abstract (EN): This chapter describes the most prominent academic efforts on compilation and synthesis of application codes written in high-level programming languages to reconfigurable architectures. The maturity of some of the compilation and mapping techniques described in Chaps. 4 and 5, and the stability of the underlying recon- figurable technologies, have enabled the emergence of commercial compilation solutions, such as the MAP compiler from SRC Computers [292] and the High-Level Compiler from Nallatech [223], both of which support the mapping of programs written in a subset of the C programming language to FPGAs. In this chapter, we distinguish between compilation efforts that target finegrained commercially available reconfigurable devices, such as well-known FPGAs, and efforts that target architectures with proprietary reconfigurable devices, typically coarse-grained devices. Despite their granularity distinction, and thus the different mapping techniques used, these efforts exhibit many commonalities. We begin with a brief historical perspective on early compilation efforts, which naturally focused on fine-grained architectures. We then describe various representative compilation efforts, highlighting their use of the transformations and mapping techniques described in the previous two chapters. We conclude by summarizing and highlighting the differences between the described compilation efforts.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 22