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An FPGA-based multi-core approach for pipelining computing stages

Title
An FPGA-based multi-core approach for pipelining computing stages
Type
Article in International Conference Proceedings Book
Year
2013
Authors
Azarian, A
(Author)
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Werner, S
(Author)
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Becker, J
(Author)
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Conference proceedings International
Pages: 1533-1540
28th Annual ACM Symposium on Applied Computing, SAC 2013
Coimbra, 18 March 2013 through 22 March 2013
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Authenticus ID: P-008-B1M
Abstract (EN): In recent years, there has been increasing interest on using task-level pipelining to accelerate the overall execution of applications mainly consisting of Producer-Consumer tasks. This paper proposes an approach to achieve pipelining execution of Producer-Consumer pairs of tasks in FPGA-based multi-core architectures. Our approach is able to speedup the overall execution of successive, data-dependent tasks, by using multiple cores and specific customization features provided by FPGAs. An important component of our approach is the use of customized inter-stage buffer schemes to communicate data and to synchronize the cores associated to the Producer-Consumer tasks. In order to improve performance, we propose a technique to optimize out-of-order Producer-Consumer pairs where the consumer uses more than once each data element produced, a behavior present in many applications (e.g., in image processing). All the schemes and optimizations proposed in this paper were evaluated with FPGA implementations. The experimental results show the feasibility of the approach in both in-order and out-of-order Producer-Consumer tasks. Furthermore, the results using our approach to task-level pipelining and a multi-core architecture reveal noticeable performance improvements for a number of benchmarks over a single core implementation without using task-level pipelining. Copyright 2013 ACM.
Language: English
Type (Professor's evaluation): Scientific
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