Compilation increasing the scheduling scope for multi-memory-FPGA-based custom computing machines

• Type: Article in International Conference Proceedings Book
• Date: 2001

Authors

João M. P. Cardoso (Author) Other; Neto, HC (Author) Other

Conference proceedings International

Title: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Pages: 523-533

11th International Conference on Field-Programmable Logic and Applications, FPL 2001

27 August 2001 through 29 August 2001

Indexing

Scopus - 1 Citation

Other information

Authenticus ID: P-008-M52

DOI: 10.1007/3-540-44687-7_54

Abstract (EN): This paper presents new achievements on the automatic mapping of abstract algorithms, written in imperative software programming languages, to custom computing machines. The reconfigurable hardware element of the target architecture consists of one field-programmable gate array coupled with one or more memories. The compilation flow exposes operation- and functional-level parallelism, and speculative execution. Such expositions are efficiently represented in a hierarchical model. In order to take full advantage of such representation, the scheduling scope is significantly improved by merging basic blocks at loop boundaries and by considering the parallel execution of exposed concurrent loops. The paper describes the scheduling technique, shows a study on the impact of the merge operation, and reveals the improvements achieved when the exposed parallelism is fully satisfied. © Springer-Verlag Berlin Heidelberg 2001.

Language: English

Type (Professor's evaluation): Scientific