Use of previously acquired positioning of optimizations for phase ordering exploration

• Type: Article in International Conference Proceedings Book
• Date: 2015

Authors

Nobre, R (Author) Other; Martins, LGA (Author) Other; João M. P. Cardoso (Author) FEUP

Conference proceedings International

Title: Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2015

Pages: 58-67

18th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2015

1 June 2015 through 3 June 2015

Indexing

Scopus - 13 Citations

Other information

Authenticus ID: P-00G-SYK

DOI: 10.1145/2764967.2764978

Abstract (EN): This paper presents a new approach to efficiently search for suitable compiler pass sequences, a challenge known as phase ordering. Our approach relies on information about the relative positions of compiler passes in compiler pass sequences previously generated for a set of functions when compiling for a specific processor. We enhanced two iterative compiler pass exploration schemes, one relying on simple sequential compiler pass insertion and other implementing an auto-tuned simulated annealing process, with a data structure that holds information about the relative positions of compiler sequences; in order to reduce the set of compiler passes considered for insertion in a given position of a given candidate compiler pass sequence to include only the passes that have a higher probability of performing well on that relative position in the compiler sequence, speeding up the exploration time as a result. We tested our approach with two different compilers and two different targets; the ReflectC and the LLVM compilers, targeting a MicroBlaze processor and a LEON3 processor, respectively. The experimental results show that we can considerably reduce the number of algorithm iterations by a factor of up to more than an order of magnitude when targeting the MicroBlaze or the LEON3, while finding compiler sequences that result in binaries that when executed on the target processor/simulator are able to outperform (i.e. use less CPU cycles) all the standard optimization levels (i.e., we compare against the most performing optimization level flag on each kernel, e.g. -O1, -O2 or -O3 in the case of LLVM) by a geometric mean performance improvement of 1.23x and 1.20x when targeting the MicroBlaze processor, and 1.94x and 2.65x when targetting the LEON3 processor; for each of the two exploration algorithms and two kernel sets considered. © 2015 ACM.

Language: English

Type (Professor's evaluation): Scientific