Techniques for Dynamically Mapping Computations to Coprocessors

• Type: Article in International Conference Proceedings Book
• Date: 2011

Authors

João Bispo (Author) Other; João M. P. Cardoso (Author) FEUP

Conference proceedings International

Title: 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011

Pages: 505-508

2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011

Cancun, Quintana Roo, 30 November 2011 through 2 December 2011

Indexing

Scopus - 1 Citation

Other information

Authenticus ID: P-008-2EN

DOI: 10.1109/ReConFig.2011.86

Abstract (EN): In embedded reconfigurable computing systems, general purpose processors (GPPs) are typically extended with coprocessors to meet specific goals, such as higher performance and/or energy savings. Coprocessors can range from specialized modules which execute a specific task to reconfigurable arrays of ALUs. This paper presents our ongoing work on techniques to dynamically offload computations being executed by a GPP to a coprocessor. We present our method for identifying repetitive instruction traces, named as Mega blocks, as well as transformations which can be applied over those Mega blocks. We also present a proof-of-concept implementation of a system which transparently moves computations from a GPP to a Specialized Reconfigurable Array (SRA). Finally, we present our current and planned work. © 2011 IEEE.

Language: English

Type (Professor's evaluation): Scientific