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Specifying Compiler Strategies for FPGA-based Systems

Title
Specifying Compiler Strategies for FPGA-based Systems
Type
Article in International Conference Proceedings Book
Year
2012
Authors
Teixeira, J
(Author)
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Nobre, R
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Diniz, PC
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Coutinho, JGF
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Luk, W
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Conference proceedings International
Pages: 192-199
20th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM)
Toronto, CANADA, APR 29-MAY 01, 2012
Other information
Authenticus ID: P-002-FAA
Abstract (EN): The development of applications for high-performance Field Programmable Gate Array (FPGA) based embedded systems is a long and error-prone process. Typically, developers need to be deeply involved in all the stages of the translation and optimization of an application described in a high-level programming language to a lower-level design description to ensure the solution meets the required functionality and performance. This paper describes the use of a novel aspect-oriented hardware/software design approach for FPGA-based embedded platforms. The design-flow uses LARA, a domain-specific aspect-oriented programming language designed to capture high-level specifications of compilation and mapping strategies, including sequences of data/computation transformations and optimizations. With LARA, developers are able to guide a design-flow to partition and map an application between hardware and software components. We illustrate the use of LARA on two complex real-life applications using high-level compilation and synthesis strategies for achieving complete hardware/software implementations with speedups of 2.5x and 6.8x over software-only implementations. By allowing developers to maintain a single application source code, this approach promotes developer productivity as well as code and performance portability.
Language: English
Type (Professor's evaluation): Scientific
No. of pages: 8
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