Parallel Implementation of K-Means Algorithm on FPGA

• Type: Article in International Scientific Journal
• Date: 2020

Authors

Leonardo A. Dias (Author) Other; João Canas Ferreira (Author) FEUP; Marcelo A. Fernandes (Author) Other

Journal

Title: IEEE Access

Vol. 8

Pages: 41071-41084

ISSN: 2169-3536

Publisher: IEEE

Indexing

ISI Web of Knowledge - 1 Citation

Scopus - 2 Citations

Other information

Authenticus ID: P-00R-WWM

DOI: 10.1109/access.2020.2976900

Abstract (EN): The K-means algorithm is widely used to find correlations between data in different application domains. However, given the massive amount of data stored, known as Big Data, the need for high-speed processing to analyze data has become even more critical, especially for real-time applications. A solution that has been adopted to increase the processing speed is the use of parallel implementations on FPGA, which has proved to be more efficient than sequential systems. Hence, this paper proposes a fully parallel implementation of the K-means algorithm on FPGA to optimize the system & x2019;s processing time, thus enabling real-time applications. This proposal, unlike most implementations proposed in the literature, even parallel ones, do not have sequential steps, a limiting factor of processing speed. Results related to processing time (or throughput) and FPGA area occupancy (or hardware resources) were analyzed for different parameters, reaching performances higher than 53 millions of data points processed per second. Comparisons to the state of the art are also presented, showing speedups of more than over a partially serial implementation.

Language: English

Type (Professor's evaluation): Scientific

No. of pages: 14