FPGA architectures for reconfigurable computing

• Tipo: Artigo em Livro de Atas de Conferência Nacional
• Data: 2007-02

Autores

José M. Ferreira (Autor) FEUP; Manuel G. Gericota (Autor) Outra; Gustavo R. Alves (Autor) Outra

Ata de Conferência Nacional

Título: Actas das III Jornadas sobre Sistemas Reconfiguráveis

Páginas: 22-25

III Jornadas sobre Sistemas Reconfiguráveis (REC'07)

Lisbon, 8 a 9 de Fevereiro de 2007

Classificação Científica

CORDIS: Ciências Tecnológicas > Engenharia > Engenharia electrotécnica

FOS: Ciências da engenharia e tecnologias > Engenharia electrotécnica, electrónica e informática

Outras Informações

Abstract (EN): To accelerate the execution of an application, repetitive logic and arithmetic computation tasks may be mapped to reconfigurable hardware, since dedicated hardware can deliver much higher speeds than those of a general-purpose processor. However, this is only feasible if the run-time reconfiguration of new tasks is fast enough, so as not to delay application execution. Currently, this is opposed by architectural constraints intrinsic to current Field-Programmable Logic Array (FPGA) architectures. Despite all new features exhibited by current FPGAs, architecturally they are still largely based on general-purpose architectures that are inadequate for the demands of reconfigurable computing. Large configuration file sizes and poor hardware and software support for partial and dynamic reconfiguration limits the acceleration that reconfigurable computing may bring to applications. The objective of this work is the identification of the architectural limitations exhibited by current FPGAs that prevent reconfigurable computing systems to achieve a high efficiency and performance and the proposal of alternatives to its resolution.

Idioma: Inglês

Tipo (Avaliação Docente): Científica

Nº de páginas: 4